1. Field of the Invention
The present invention relates to voltage storage circuits for use, for example, in analog-to-digital converters for storing an applied analog value prior to conversion into its digital equivalent.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a previously-considered voltage storage circuit comprising an input switch element 1, a storage capacitor 2 and a high-impedance unity-gain amplifier element 3. Initially, with the switch element 1 in the closed position, an analog input voltage V.sub.i applied between input terminals of the circuit is supplied to the storage capacitor 2 so that the potential difference between the plates of the storage capacitor tracks the input voltage V.sub.i. At a predetermined moment in time t.sub.switch the input switch element 1 is switched to the open position, with the result that the potential difference between the capacitor plates immediately prior to such switching is stored until such time as the input switch element 1 is closed again. During the period in which the switch element is in the open position the stored voltage is reproduced between output terminals of the circuit as an output voltage V.sub.o, the amplifier element 3 serving to prevent loading of the storage capacitor by circuitry connected with the output terminals.
FIG. 2 shows an input portion of the amplifier element 3 in more detail. This input portion includes an FET input transistor 33 having a drain electrode connected to a positive supply line V.sub.dd of the element, a source electrode connected by way of a current source 32 to a negative supply line V.sub.ss of the element, and a gate electrode connected to one plate (the upper plate in FIG. 1) of the storage capacitor 2. It will be appreciated that the FET input transistor 33 is connected in the so-called source follower configuration.
Further circuitry, not shown in FIG. 2, is normally interposed between the source electrode of the FET input transistor 33 and an output of the element for buffering the source electrode potential to produce the output potential V.sub.o.
In use of the amplifier element 3 of FIG. 2, the current source 32 causes a current to flow in the drain-source channel of the FET input transistor 33, with the result that the source electrode potential V.sub.s thereof follows the gate electrode potential and hence the stored potential V.sub.c of the upper plate of the storage capacitor 2. Thus, the input portion of the amplifier element 3 has a voltage gain of substantially unity, although in practice the source electrode potential V.sub.s is always slightly less than the potential V.sub.c of the upper plate of the storage capacitor 2.
Because the input portion employs an FET input transistor the gate current of which is very small, the input impedance of the element is very high. Thus, after the input switch element 1 of the voltage storage circuit of FIG. 1 has been opened, the storage capacitor is not discharged to a significant extent by the amplifier element 3.
The amplifier element 3 of FIG. 2 suffers, however, from a disadvantage arising from charge injection into its input portion from the storage capacitor 2 (or vice versa) when the potential of the upper plate V.sub.c of the storage capacitor 2 is changed. Although after the input switch element 1 has been opened, no such change in the upper plate potential will normally result, as explained later in the present specification the upper plate potential V.sub.c unavoidably changes at the moment t.sub.switch of opening of the input switch element 1 due to charge injection at that moment by the input switch element 1 itself. Such charge injection by the input switch element 1 leads to a small, but at high precision significant, change in the stored voltage in the storage capacitor 2 and hence brings about a change in the potential V.sub.c of the upper plate thereof at the moment the switch element is opened.
The reasons for charge injection at the amplifier element input portion, in response to changes in the upper plate potential of the storage capacitor 2, will now be explained. As shown in FIG. 2, the FET input transistor 33 unavoidably has small parasitic capacitances between its electrodes, there being a gate-source parasitic capacitance C.sub.gs between the gate and source electrodes, a gate-drain parasitic capacitance C.sub.gd between the gate and drain electrodes, and a drain-source parasitic capacitance C.sub.ds between the drain and source electrodes. Whenever the potentials of these three electrodes change relative to one another, charge must flow into or out of the parasitic capacitances, and it is the combination of these charge flows which leads to charge injection to/from the amplifier element input portion.
In the FIG. 2 amplifier element, because the input transistor 33 is connected in the above-mentioned source follower configuration, the gate-source potential thereof is substantially constant, irrespective of the upper plate potential V.sub.c of the storage capacitor 2, so that charge injection due to the gate-source parasitic capacitance C.sub.gs can normally be neglected.
However, the gate-drain potential and the drain-source potential of the input transistor 33, being V.sub.dd -V.sub.c and V.sub.dd -V.sub.s respectively, are not constant and vary in dependence upon the upper plate potential V.sub.c. Thus, whenever V.sub.c is changed, charge must flow into or out of the gate-drain parasitic capacitance C.sub.gd and the drain-source parasitic capacitance C.sub.ds, in either case causing charge to flow into or out of the input portion of the amplifier element.
When the input switch element is open, the charge that flows must either charge or discharge the storage capacitor 2, depending upon the direction of flow. Such charge or discharge unavoidably leads to an error in the stored voltage between the plates of the storage capacitor 2.
The effects of the parasitic capacitances of the input portion of the amplifier element are particularly severe when the capacitance of the storage capacitor 2 is not large relative to the capacitances of the parasitic capacitances themselves, which may be the case for example when it is desired to reduce acquisition time of the voltage storage circuit.